What Is Voltage Divider Bias Method
Voltage Divider Bias is the most widely used method of providing biasing and stabilization to a transistor. In this method, two resistances R1 and R2 are connected across the supply voltage VCC (See Fig. 9.24) and provide biasing. The emitter resistance RE provides stabilization. The name ‘‘voltage divider’’ comes from the voltage divider formed by R1 and R2. The voltage drop across R2 forward biases the base emitter junction. This causes the base current and hence collector current flow in the zero signal conditions.
Circuit Analysis Of Voltage Divider Bias
Suppose that the current flowing through resistance R1 is I1. As base current IB is very small, therefore, it can be assumed with reasonable accuracy that current flowing through R2 is also I1
(i) Collector current IC:
It is clear from exp. (i) above that IC does not at all depend upon β. Though IC depends upon VBE but in practice V2>>VBE so that IC is practically independent of VBE. Thus IC in this circuit is almost independent of transistor parameters and hence good stabilisation is ensured. It is due to this reason that voltage divider bias has become universal method for providing transistor biasing.
(ii) Collector-emitter voltage VCE.
Applying Kirchhoff ‘s voltage law to the collector side,
VCC = IC RC+VCE + IE RE
In this circuit, excellent stabilisation is provided by RE . Consideration of eq. (I) reveals this fact.
V2 = VBE + IC RE
Suppose the collector current IC increases due to rise in temperature. This will cause the voltage drop across emitter resistance RE to increase. As voltage drop across R2 (i.e. V2 ) is *independent of
IC, therefore, VBE decreases. This in turn causes IB to decrease. The reduced value of IB tends to restore IC to the original value.
It can be shown mathematically (See Art. 9.13) that stability factor of the circuit is given by
This is the smallest possible value of S and leads to the maximum possible thermal stability. Due to
design **considerations, R0 / RE has a value that cannot be neglected as compared to 1. In actual
practice, the circuit may have stability factor around 10.
Example 9.19. Fig. 9.25 (i) shows the voltage divider bias method. Draw the d.c. load line and determine the operating point. Assume the transistor to be of silicon.
Solution. d.c. load line. The collector-emitter voltage VCE is given by :
This locates the second point A (OA = 5 mA) of the load line on the collector current axis. By
joining points A and B, the d.c. load line AB is constructed as shown in Fig. 9.25 (ii).
Example 9.20. Determine the operating point of the circuit shown in the previous problem by
using Thevenin’s theorem.
Solution. The circuit is redrawn and shown in Fig. 9.26 (i) for facility of reference. The d.c. circuit to the left of base terminal B can be replaced by Thevenin’s equivalent circuit shown in Fig. 9.26 (ii). Looking to the left from the base terminal B [See Fig. 9.26 (i)], Thevenin’s equivalent voltage E0 is given by :
Example 9.21. A transistor uses voltage divider method of biasing. R1= 50 kΩ, R2= 10 kΩ and RE= 1kΩ. If VCC = 12 V, find :
(i) the value of IC ; given VBE = 0.1V (ii) the value of IC ; given VBE = 0.3V. Comment on the result.
Comments. From the above example, it is clear that although VBE varies by 300%, the value of
IC changes only by nearly 10%. This explains that in this method, IC is almost independent of transistor parameter variations.
Example 9.22. Calculate the emitter current in the voltage divider circuit shown in Fig. 9.27. Also find the value of VCE and collector potential VC.
Stability Factor For Potential Divider Bias
We have already seen (See example 9.20) how to replace the voltage divider circuit of potential
divider bias by Thevenin’s equivalent circuit. The resulting voltage divider bias circuit is redrawn in
Fig. 9.28 in order to find the stability factor S for this biasing circuit. Referring to Fig. 9.28 and
applying Kirchhoff’s voltage law to the base circuit, we have,
Eq. (ii) gives the formula for the stability factor S for the potential divider bias circuit. The
following points may be noted carefully :
(i) For greater thermal stability, the value of S should be small. This can be achieved by making
R0/RE small. If R0 /RE is made very small, then it can be neglected as compared to 1.
This is the ideal value of S and leads to the maximum thermal stability.
(ii) The ratio *R0 /RE can be made very small by decreasing R0 and increasing RE. Low value of R0 can be obtained by making R2 very small. But with low value of R2, current drawn from VCC will be large. This puts restriction on the choice of R0. Increasing the value of RE requires greater VCC in order to maintain the same zero signal collector current. Due to these limitations, a compromise is
made in the selection of the values of R0 and RE. Generally, these values are so selected that S j 10.
Example 9.23. For the circuit shown in Fig. 9.29 (i), find the operating point. What is the stability factor of the circuit ? Given that β = 50 and VBE = 0.7V
Solution. Fig. 9.29 (i) shows the circuit of potential divider bias whereas Fig. 9.29 (ii) shows it
with potential divider circuit replaced by Thevenin’s equivalent circuit.
However, by replacing the potential divider circuit by Thevenin’s equivalent circuit, the expression for IC can be found more accurately. If not mentioned in the problem, any one of the two methods
can be used to obtain the solution.
Example 9.24. The circuit shown in Fig. 9.30 (i) uses silicon transistor having β = 100. Find
the operating point and stability factor
Solution. Fig. 9.30 (i) shows the circuit of potential divider bias whereas Fig. 9.30 (ii) shows it
with potential divider circuit replaced by Thevenin’s equivalent circuit.
Design of Transistor Biasing Circuits
(For low powered transistors) In practice, the following steps are taken to design transistor biasing and stabilisation circuits :
Step 1. It is a common practice to take RE= 500 − 1000Ω. Greater the value of RE, better is the
stabilisation. However, if RE is very large, higher voltage drop across it leaves reduced voltage drop across the collector load. Consequently, the output is decreased. Therefore, a compromise has to be made in the selection of the value of RE
Step 2. The zero signal current IC is chosen according to the signal swing. However, in the initial stages of most transistor amplifiers, zero signal IC = 1mA is sufficient. The major advantages of selecting this value are :
(i) The output impedance of a transistor is very high at 1mA. This increases the voltage gain.
(ii) There is little danger of overheating as 1mA is quite a small collector current. It may be noted here that working the transistor below zero signal IC = 1mA is not advisable because of strongly non-linear transistor characteristics.
Step 3. The values of resistances R1 and R2 are so selected that current I1 flowing through R1 and
R2 is atleast 10 times IB i.e. I1 ≥ 10 IB . When this condition is satisfied, good stabilisation is achieved.
Step 4. The zero signal IC should be a little more (say 20%) than the maximum collector current
swing due to signal. For example, if collector current change is expected to be 3mA due to signal,
then select zero signal IC~ 3.5 mA. It is important to note this point. Selecting zero signal IC below this value may cut off a part of negative half-cycle of a signal. On the other hand, selecting a value much above this value (say 15mA) may unnecessarily overheat the transistor, resulting in wastage of battery power. Moreover, a higher zero signal IC will reduce the value of RC (for same VCC), resulting in reduced voltage gain.
Example 9.25. In the circuit shown in Fig. 9.31, the operating point is chosen such that IC = 2mA, VCE = 3V. If RC = 2.2 kΩ, VCC = 9V and β = 50, determine the values of R1, R2 and RE. Take VBE = 0.3V and I1 = 10IB
Example 9.26. An npn transistor circuit (See Fig. 9.32) has α = 0.985 and VBE = 0.3V. If VCC = 16V, calculate R1 and RC to place Q point at IC = 2mA, VCE = 6 volts.
Example 9.27. Calculate the exact value of emitter current in the circuit shown in Fig. 9.33 (i).
Assume the transistor to be of silicon and β = 100.
Solution. In order to obtain accurate value of emitter current IE, we shall replace the bias portion
of the circuit shown in Fig. 9.33 (i) by its Thevenin’s equivalent. Fig. 9.33 (ii) shows the desired circuit.Looking from the base terminal B to the left, Thevenin’s voltage E0 is given by :
Again looking from the base terminal B to the left, Thevenin’s resistance R0 is given by;
Example 9.28. The potential divider circuit shown in Fig. 9.34 has the values as follows:
IE= 2mA, IB= 50µA, VBE = 0.2V, RE= 1kΩ, R2= 10 kΩ and VCC = 10V. Find the value of R1.
Solution. In this problem, we shall consider that currents through R1 and R2 are different, although in practice this difference is very small.
Example 9.29. Fig. 9.35 shows the potential divider method of biasing. What will happen if
(i) resistance R2 is shorted (ii) resistance R2 is open-circuited
(iii) resistance R1 is shorted (iv) resistance R1 is open ?
(i) If resistance R2 is shorted, the base will be grounded. It will be left without forward bias and the transistor will be cut off i.e., output will be zero.
(ii) If resistance R2 is open, the forward bias will be very high. The collector current will be very high while collector-emitter voltage will be very low.
(iii) If resistance R1 is shorted, the transistor will be in saturation due to excessive forward bias. The base will be at VCC and emitter will be only slightly below VCC.
(iv) If R1 is open, the transistor will be without forward bias. Hence the transistor will be cut off i.e. output will be zero.
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