Transmitter is the electronic unit that accepts the information signal to be transmitted and converts it to an RF signal capable of being transmitted over long distances. Every transmitter has four basic requirements.
1. It must generate a carrier signal of the correct frequency at a desired point in the spectrum.
2. It must provide some form of modulation that causes the information signal to modify the carrier signal.
3. It must provide sufficient power amplification to ensure that the signal level is high enough to carry over the desired distance.
4. It must provide circuits that match the impedance of the power amplifier to that of the antenna for maximum transfer of power.
the simplest transmitter is a single-transistor oscillator connected directly to an antenna. The oscillator generates the carrier and can be switched off and on by a telegraph key to produce the dots and dashes of the International Morse code. Information transmitted in this way is referred to as continuous-wave (CW) transmission. Such a transmitter is rarely used today, for the Morse code is nearly extinct and the oscillator power is too low for reliable communication. Nowadays transmitter such as this are built only by amateur (ham) radio operators for what is called QRP or low-power operation for personal hobby communication.
The CW transmitter can be greatly improved by simply adding a power amplifier to it, as illustrated in Fig. 8-1. The oscillator is still keyed off and on to produce dots and dashes, and the amplifier increases the power level of the signal. The result is a stronger signal that carries farther and produces more reliable transmission. The basic oscillator-amplifier combination shown in Fig. 8-1 is the basis for virtually all radio transmitter. Many other circuits are added depending on the type of modulation used, the power level, and other considerations.
Fig. 8-2 shows an AM transmitter using high-level modulation. An oscillator, in most applications a crystal oscillator, generates the final carrier frequency. The carrier signal is then fed to a buffer amplifier whose primary purpose is to isolate the oscillator from the remaining power amplifier stages. The buffer amplifier usually operates at the class A level and provides a modest increase in power output. The main purpose of the buffer amplifier is simply to prevent load changes in the power amplifier stages or in the antenna from causing frequency variations in the oscillator.
The signal from the buffer amplifier is applied to a class C driver amplifier designed to provide an intermediate level of power amplification. The purpose of this circuit is to generate sufficient output power to drive the final power amplifier stage. The final power amplifier, normally just referred to as the final, also operates at the class C level at very high power. The actual amount of power depends on the application. For example, in a CB transmitter, the power input is only 5 W. However, AM radio stations operate at much higher powers—say, 250, 500, 1000, 5000, or 50,000 W—and the video transmitter at a TV station operates at even higher power levels. Cell phone base stations operate at the 30- to 40-W level.
All the RF circuits in the transmitter are usually solid-state; i.e., they are implemented with either bipolar transistors or metal-oxide semiconductor field-effect transistors (MOSFETs). Although bipolar transistors are by far the most common type, the use of MOSFETs is increasing because they are now capable of handling high power at high frequencies. Transistors are also typically used in the final as long as the power level does not exceed several hundred watts. Individual RF power transistors can handle up to about 800 W. Many of these can be connected in parallel or in push-pull configurations to increase the power-handling capability to many kilowatts. For higher power levels, vacuum tubes are still used in some transmitter, but rarely in new designs. Vacuum tubes function into the VHF and UHF ranges, with power levels of 1 kW or more.
Now, assume that the AM transmitter shown in Fig. 8-2 is a voice transmitter. The input from the microphone is applied to a low-level class A audio amplifier, which boosts the small signal from the microphone to a higher voltage level. (One or more stages of amplification could be used.) The voice signal is then fed to some form of speech-processing (filtering and amplitude control) circuit. The filtering ensures that only voice frequencies in a certain range are passed, which helps to minimize the bandwidth occupied by the signal. Most communication transmitter limit the voice frequency to the 300- to 3000-Hz range, which is adequate for intelligible communication. However, AM broadcast stations offer higher fidelity and allow frequencies up to 5 kHz to be used. In practice, many AM stations modulate with frequencies up to 7.5 kHz, and even 10 kHz, since the FCC uses alternate channel assignments within a given region and the outer sidebands are very weak, so no adjacent channel interference occurs.
Final power amplifier Speech processing Figure 8-2 An AM transmitter using high-level collector modulation. Carrier oscillator Driver Buffer amplifier Final power amplifier Microphone Audio amplifier Speech processing Driver Modulation amplifier Radio Transmitter 239 Speech processors also contain a circuit used to hold the amplitude to some maximum level. High-amplitude signals are compressed and lower-amplitude signals are given more amplification. The result is that over modulation is prevented, yet the transmitter operates as close to 100 percent modulation as possible. This reduces the possibility of signal distortion and harmonics, which produce wider sidebands that can cause adjacent channel interference, but maintains the highest possible output power in the sidebands. After the speech processor, a driver amplifier is used to increase the power level of the signal so that it is capable of driving the high-power modulation amplifier.
Low-Level FM Transmitter
In low-level modulation, modulation is performed on the carrier at low power levels, and the signal is then amplified by power amplifiers. This arrangement works for both AM and FM. FM transmitter using this method are far more common than low-level AM transmitter. Fig. 8-3 shows the typical configuration for an FM or PM transmitter. The indirect method of FM generation is used. A stable crystal oscillator is used to generate the carrier signal, and a buffer amplifier is used to isolate it from the remainder of the circuitry. The carrier signal is then applied to a phase modulator such as those discussed in article. 6.
In the AM transmitter of Fig. 8-2, high-level or collector modulation (plate modulation in a tube) is used. As stated previously, the power output of the modulation amplifier must be one-half the input power of the RF amplifier. The high-power modulation amplifier usually operates with a class AB or class B push-pull configuration to achieve these power levels.
The voice input is amplified and processed to limit the frequency range and prevent over deviation. The output of the modulator is the desired FM signal. Most FM transmitters are used in the VHF and UHF range. Because crystals are not available for generating those frequencies directly, the carrier is usually generated at a frequency considerably lower than the final output frequency. To achieve the desired output frequency, one or more frequency multiplier stages are used. A frequency multiplier is a class C amplifier whose output frequency is some integer multiple of the input frequency. Most frequency multipliers increase the frequency by a factor of 2, 3, 4, or 5. Because they are class C amplifiers, most frequency multipliers also provide a modest amount of power amplification. Not only does the frequency multiplier increase the carrier frequency to the desired output frequency, but also it multiplies the frequency deviation produced by the modulator. Many frequency and phase modulators generate only a small frequency shift, much lower than the desired final deviation. The design of the transmitter must be such that the frequency multipliers will provide the correct amount of multiplication not only for the carrier frequency but also for the modulation deviation. After the frequency multiplier stage, a class C driver amplifier is used to increase the power level sufficiently to operate the final power amplifier, which also operates at the class C level.
Most FM communication transmitter operate at relatively low power levels, typically less than 100 W. All the circuits, even in the VHF and UHF range, use transistors. For power levels beyond several hundred watts, vacuum tubes must be used. The final amplifier stages in FM broadcast transmitters typically use large vacuum tube class C amplifiers. In FM transmitter operating in the microwave range, klystrons, magnetrons, and traveling-wave tubes are used to provide the final power amplification
A typical single-sideband (SSB) transmitter is shown in Fig. 8-4. An oscillator signal generates the carrier, which is then fed to the buffer amplifier. The buffer amplifier supplies the carrier input signal to the balanced modulator. The audio amplifier and speech-processing circuits described previously provide the other nput to the balanced modulator. The balanced modulator output—a DSB signal—is then fed to a sideband filter that selects either the upper or lower sideband. Following this, the SSB signal is fed to a mixer circuit, which is used to convert the signal to its final operating frequency. Mixer circuits, which operate as simple amplitude modulators, are used to convert a lower frequency to a higher one or a higher frequency to a lower one. (Mixers are discussed more fully in Chap. 9.)
Typically, the SSB signal is generated at a low RF. This makes the balanced modulator and filter circuits simpler and easier to design. The mixer translates the SSB signal to a higher desired frequency. The other input to the mixer is derived from a local oscillator set at a frequency that, when mixed with the SSB signal, produces the desired operating frequency. The mixer can be set up so that the tuned circuit at its output selects either the sum or the difference frequency. The oscillator frequency must be set to provide the desired output frequency. For fixed-channel operation, crystals can be used in this local oscillator. However, in some equipment, such as that used by hams, a variable frequency oscillator(VFO) is used to provide continuous tuning over the desired range. In most modern communication equipment, a frequency synthesizer is used to set the final output frequency
The output of the mixer in Fig. 8-4 is the desired final carrier frequency containing the SSB modulation. It is then fed to linear driver and power amplifiers to increase the power level as required. Class C amplifiers distort the signal and therefore cannot be used to transmit SSB or low-level AM of any kind, including DSB. Class A or AB linear amplifiers must be used to retain the information content in the AM signal.
Most modern digital radios such as cell phones use DSP to produce the modulation and related processing of the data to be transmitted. Refer to Fig. 8-5. The serial data representing the data to be transmitted is sent to the DSP, which then generates two data streams that are then converted to RF for transmission. The data paths from the DSP chip are sent to DACs where they are translated to equivalent analog signals.
The analog signals are filtered in a low-pass filter (LPF) and then applied to mixers that will up-convert them to the final output frequency. The mixers receive their second inputs from an oscillator or a frequency synthesizer that selects the operating frequency. Note that the oscillator signals are in quadrature; i.e., one is shifted 90° from the other. One is a sine wave, and the other is a cosine wave. The upper signal is referred to as the in-phase (I) signal and the other as the quadrature (Q) signal. The output signals from the mixers are then added, and the result is amplified and transmitted by the power amplifier (PA). Two quadrature signals are needed at the receiver to recover the signal and demodulate it in a DSP chip. This configuration works for any type of modulation as all of the modulation is done with mathematical algorithms. You will learn more about this technique in Chap. 11.
The starting point for all transmitter is carrier generation. Once generated, the carrier can be modulated, processed in various ways, amplified, and finally transmitted. The source of most carriers in modern transmitter is a crystal oscillator. PLL frequency synthesizers in which a crystal oscillator is the basic stabilizing reference are used in applications requiring multiple channels of operation
Most radio transmitter are licensed by the FCC either directly or indirectly to operate not only within a specific frequency band but also on predefined frequencies or channels. Deviating from the assigned frequency by even a small amount can cause interference with signals on adjacent channels. Therefore, the transmitter carrier generator must be very precise, operating on the exact frequency assigned, often within very close tolerances. In some radio services, the frequency of operation must be within 0.001 percent of the assigned frequency. In addition, the transmitter must remain on the assigned frequency. It must not drift off or wander from its assigned value despite the many operating conditions, such as wide temperature variations and changes in power supply voltage, that affect frequency. The only oscillator capable of meeting the precision and stability demanded by the FCC is a crystal oscillator.
A crystal is a piece of quartz that has been cut and ground into a thin, flat wafer and mounted between two metal plates. When the crystal is excited by an ac signal across its plates, it vibrates. This action is referred to as the piezoelectric effect. The frequency of vibration is determined primarily by the thickness of the crystal. Other factors influencing frequency are the cut of the crystal, i.e., the place and angle of cut made in the base quartz rock from which the crystal was derived, and the size of the crystal wafer.
Crystals frequencies range from as low as 30 kHz to as high as 150 MHz. As the crystal vibrates or oscillates, it maintains a very constant frequency. Once a crystal has been cut or ground to a particular frequency, it will not change to any great extent even with wide voltage or temperature variations. Even greater stability can be achieved by mounting the crystal in sealed, temperature-controlled chambers known as crystal ovens. These devices maintain an absolute constant temperature, ensuring a stable output frequency.
As you saw in Chap. 4, the crystal acts as an LC tuned circuit. It can emulate a series or parallel LC circuit with a Q as high as 30,000. The crystal is simply substituted for the coil and capacitor in a conventional oscillator circuit. The end result is a very precise, stable oscillator. The precision, or stability, of a crystal, is usually expressed in parts per million (ppm). For example, to say that a crystal with a frequency of 1 MHz has a precision of 100 ppm means that the frequency of the crystal can vary from 999,900 to 1,000,100 Hz. Most crystals have tolerance and stability values in the 10- to 1000-ppm range. Expressed as a percentage, the precision is (100/1,000,000) x 100 = 0.0001 x 100 = 0.01 percent
You can also use ratio and proportion to figure the frequency variation for a crystal with a given precision. For example, a 24-MHz crystal with a stability of 650 ppm has a maximum frequency variation Δf of 50 (1,000,000)/(24,000,000). Thus, Δf 550(24,000,000)/1,000,000 = 24×50 = 1200 Hz or 1200 Hz.
Example 8.1 What are the maximum and minimum frequencies of a 16-MHz crystal with a stability of 200 ppm? The frequency can vary as much as 200 Hz for every 1 MHz of frequency or 200 x 16 = 3200 Hz. The possible frequency range is
However, the simplest way to convert from percentage to ppm is to convert the percentage value to its decimal form by dividing by 100, or moving the decimal point two places to the left, and then multiplying by 106 , or moving the decimal point six places to the right. For example, the ppm stability of a 5-MHz crystal with a precision of 0.005 percent is found as follows. First, put 0.005 percent in decimal form: 0.005 percent = 0.00005. Next, multiply by 1 million: 0.00005 x 1,000,000 = 50 ppm
A radio transmitter uses a crystal oscillator with a frequency of 14.9 MHz and a frequency multiplier chain with factors of 2, 3, and 3. The crystal has a stability of +-300 ppm.
a. Calculate the transmitter output frequency.
Typical Crystal Oscillator Circuits
The most common crystal oscillator is a Colpitts type, in which the feedback is derived from the capacitive voltage divider made up of C1 and C2. An emitter-follower version is shown in Fig. 8-6. Again, the feedback comes from the capacitor voltage divider C1–C2. The output is taken from the emitter, which is untuned. Most oscillators of this type operate as class A amplifiers with a sine wave output. JFETs are also widely used in discrete component amplifiers.
Occasionally you will see a capacitor in series or in parallel with the crystal (not both), as shown in Fig. 8-6. These capacitors can be used to make minor adjustments in the crystal frequency.
As discussed previously, it is not possible to affect large frequency changes with series or shunt capacitors, but they can be used to make fine adjustments. The capacitors are called crystal pulling capacitors, and the whole process of fine-tuning a crystal is sometimes referred to as rubbering. When the pulling capacitor is a varactor, FM or FSK can be produced. The analog or binary modulating signal varies the varactor capacitance that, in turn, shifts the crystal frequency.
The main problem with crystals is that their upper-frequency operation is limited. The higher the frequency, the thinner the crystal must be to oscillate at that frequency. At an upper limit of about 50 MHz, the crystal is so fragile that it becomes impractical to use. However, over the years, operating frequencies have continued to move upward as a result of the quest for more frequency space and greater channel capacity, and the FCC has continued to demand the same stability and precision that are required at the lower frequencies. One way to achieve VHF, UHF, and even microwave frequencies using crystals is by employing frequency multiplier circuits, as described earlier. The carrier oscillator operates on a frequency less than 50 MHz, and multipliers raise that frequency to the desired level. For example, if the desired operating frequency is 163.2 MHz and the frequency multipliers multiply by a factor of 24, the crystal frequency must be 163.2/24 = 6.8 MHz.
Another way to achieve crystal precision and stability at frequencies above 50 MHz is to use overtone crystals. An overtone crystal is cut in a special way so that it optimizes its oscillation at an overtone of the basic crystal frequency. An overtone is like a harmonic as it is usually some multiple of the fundamental vibration frequency. However, the term harmonic is usually applied to electric signals, and the term overtone refers to higher mechanical vibration frequencies. Like a harmonic, an overtone is usually some integer multiple of the base vibration frequency. However, most overtones are slightly more or slightly less than the integer value. In a crystal, the second harmonic is the first overtone, the third harmonic is the second overtone, and so on. For example, a crystal with a fundamental frequency of 20 MHz would have a second harmonic or first overtone of
40 MHz, and a third harmonic or second overtone of 60 MHz.
The term overtone is often used as a synonym for harmonic. Most manufacturers refer to their third overtone crystals as third harmonic crystals.
The odd overtones are far greater in amplitude than the even overtones. Most overtone crystals oscillate reliably at the third or fifth overtone of the frequency at which the crystal is originally ground. There are also seventh-overtone crystals. Overtone crystals can be obtained with frequencies up to about 250 MHz. A typical overtone crystal oscillator may use a crystal cut for a frequency of, say, 16.8 MHz, and optimized for overtone service will have a third-overtone oscillation at 3 x 16.8 = 50.4 MHz. The tuned output circuit made up of L1 and C1 will be resonant at 50.4 MHz.
Most crystal oscillators are circuits built into other integrated circuits. The crystal is external to the IC. Another common form is that shown in Fig. 8-7, where the crystal and oscillator circuit are fully packaged together as an IC. Both sine and square output versions are available.
There are many different versions of these packaged crystal oscillators. These are the basic crystal oscillator (XO), the voltage-controlled crystal oscillator (VCXO), the temperature-compensated crystal oscillator (TCXO), and the oven-controlled crystal oscillator (OCXO). The selection depends upon the desired degree of frequency stability required by the application. The basic XO has a stability in the tens of ppm
A VCXO uses a varactor in series or parallel with the crystal (Fig. 8-6) to vary the crystal frequency over a narrow range with an external DC voltage.
Improved stability is obtained in the TCXO, which uses a feedback network with a thermistor to sense temperature variations, which in turn controls a voltage variable capacitor (VVC) or varactor to pull the crystal frequency to some desired value. TCXOs can achieve stability values of 60.2 to 62 ppm.
An OCXO packages the crystal and its circuit in a temperature-controlled oven that holds the frequency stable at the desired frequency. A thermistor sensor in a feedback network varies the temperature of a heating element in the oven. Stabilities in the 1 x 10-8 or better can be obtained.
Frequency synthesizers are variable-frequency generators that provide the frequency stability of crystal oscillators but with the convenience of incremental tuning over a broad frequency range. Frequency synthesizers usually provide an output signal that varies in fixed frequency increments over a wide range. In a transmitter, a frequency synthesizer provides basic carrier generation for channelized operation. Frequency synthesizers are also used in receivers as local oscillators and perform the receiver tuning function.
Using frequency synthesizers overcomes certain cost and size disadvantages associated with crystals. Assume, e.g., that a transmitter must operate on 50 channels. Crystal stability is required. The most direct approach is simply to use one crystal per frequency and add a large switch. Although such an arrangement works, it has major disadvantages. Crystals are expensive, ranging from $1 to $10 each, and even at the lowest price, 50 crystals may cost more than all the rest of the parts in the transmitter. The same 50 crystals would also take up a great deal of space, possibly occupying more than10 times the volume of all the rest of the transmitter parts. With a frequency synthesizer, only one crystal is needed, and the requisite number of channels can be generated by
using a few tiny ICs.
Over the years, many techniques have been developed for implementing frequency synthesizers with frequency multipliers and mixers. Today, however, most frequency synthesizers use some variation of the phase-locked loop (PLL). A newer technique called digital signal synthesis (DSS) is becoming more popular as integrated-circuit technology has made high-frequency generation practical.
Phase-Locked Loop Synthesizers
An elementary frequency synthesizer based on a PLL is shown in Fig. 8-8. Like all phase-locked loops, it consists of a phase detector, a low-pass filter, and a VCO. The input to the phase detector is a reference oscillator. The reference oscillator is normally crystal controlled to provide high-frequency stability. The frequency of the reference oscillator sets the increments in which the frequency may be changed. Note that the VCO output is not connected directly back to the phase detector, but applied to a frequency divider first. A frequency divider is a circuit whose output frequency is some integer submultiple of the input frequency. A divide-by-10 frequency synthesizer produces an output frequency that is one-tenth of the input frequency. Frequency dividers can be easily implemented with digital circuits to provide any integer value of frequency division.
In the PLL in Fig. 8-8, the reference oscillator is set to 100 kHz (0.1 MHz). Assume that the frequency divider is initially set for a division of 10. For a PLL to become locked or synchronized, the second input to the phase detector must be equal in frequency to the reference frequency; for this PLL to be locked, the frequency divider output must be 100 kHz. The VCO output has to be 10 times higher than this, or 1 MHz. One way to look at this circuit is as a frequency multiplier: The 100-kHz input is multiplied by 10 to produce the 1-MHz output. In the design of the synthesizer, the VCO frequency is set to 1 MHz so that when it is divided, it will provide the 100-kHz input signal required by the phase detector for the locked condition. The synthesizer output is the output of the VCO. What has been created, then, is a 1-MHz signal source. Because the PLL is locked to the crystal reference source, the VCO output frequency has the same stability as that of the crystal oscillator. The PLL will track any frequency variations, but the crystal is very stable and the VCO output is as stable as that of the crystal reference oscillator.
To make the frequency synthesizer more useful, some means must be provided to vary its output frequency. This is done by varying the frequency division ratio. Through various switching techniques, the flip-flops in a frequency divider can be arranged to provide any desired frequency division ratio. In the most sophisticated circuits, a microprocessor generates the correct frequency division ratio based on software inputs.
Varying the frequency division ratio changes the output frequency. For example, in the circuit in Fig. 8-8, if the frequency division ratio is changed from 10 to 11, the VCO output frequency must change to 1.1 MHz. The output of the divider then remains at 100 kHz (1,100,000/11 = 100,000), as necessary to maintain a locked condition. Each incremental change in frequency division ratio produces an output frequency change of 0.1 MHz. This is how the frequency increment is set by the reference oscillator.
A more complex PLL synthesizer, a circuit that generates VHF and UHF frequencies over the 100- to 500-MHz range, is shown in Fig. 8-9. This circuit uses a FET oscillator to generate the carrier frequency directly. No frequency multipliers are needed. The output of the frequency synthesizer can be connected directly to the driver and power amplifiers in the transmitter. This synthesizer has an output frequency in the 390-MHz range, and the frequency can be varied in 30-kHz increments above and below that frequency.
The VCO circuit for the synthesizer in Fig. 8-9 is shown in Fig. 8-10. The frequency of this LC oscillator is set by the values of L1, C1, C2 and the capacitances of the varactor diodes D1 and D2, Ca and Cb, respectively. The dc voltage applied to the varactors changes the frequency. Two varactors are connected back to back, and thus the total effective capacitance of the pair is less than either individual capacitance. Specifically, it is equal to the series capacitance CS, where CS= CaCb/(Ca 1 Cb). If D1 and D2 are identical, CS = Ca/2. A negative voltage with respect to ground is required to reverse bias the diodes. Increasing the negative voltage increases the reverse bias and decreases the capacitance. This, in turn, increases the oscillator frequency.
Using two varactors allows the oscillator to produce higher RF voltages without the problem of the varactors becoming forward-biased. If a varactor, which is a diode, becomes forward-biased, it is no longer a capacitor. High voltages in the tank circuit of the oscillator can sometimes exceed the bias voltage level and cause forward conduction. When forward conduction occurs, rectification takes place, producing a dc voltage that changes the dc tuning voltage from the phase detector and loop filter. The result is called phase noise. With two capacitors in series, the voltage required to forward-bias the combination is double that of one varactor. An additional benefit is that two varactors in series produce a more linear variation of capacitance with voltage than one diode. The
dc frequency control voltage is, of course, derived by filtering the phase detector output with the low-pass loop filter.
In most PLLs, the phase detector is a digital circuit rather than a linear circuit, since the inputs to the phase detector are usually digital. Remember, one input comes from the output of the feedback frequency divider chain, which is certainly digital, and the other comes from the reference oscillator. In some designs, the reference oscillator frequency is also divided down by a digital frequency divider to achieve the desired frequency step increment. This is the case in Fig. 8-9. Since the synthesizer frequency can be stepped in increments of 30 kHz, the reference input to the phase detector must be 30 kHz. This is derived from a stable 3-MHz crystal oscillator and a frequency divider of 100.
The design shown in Fig. 8-9 uses an exclusive-OR gate as a phase detector. Recall that an exclusive-OR (XOR) gate generates a binary 1 output only if the two inputs are complementary; otherwise, it produces a binary 0 output.
Fig. 8-11 shows how the XOR phase detector works: Remember that the inputs to a phase detector must have the same frequency. This circuit requires that the inputs have a 50 percent duty cycle. The phase relationship between the two signals determines the output of the phase detector. If the two inputs are exactly in phase with each other, the XOR output will be zero, as Fig. 8-11(b) shows. If the two inputs are 180° out of phase with each other, the XOR output will be a constant binary 1 [see Fig. 8-11(c)]. Any other phase relationship will produce output pulses at twice the input frequency. The duty cycle of these pulses indicates the amount of phase shift. A small phase shift produces narrow pulses; a larger phase shift produces wider pulses. Fig. 8-11(d) shows a 90° phase shift.
The output pulses are fed to the loop filter (Fig. 8-9), an op amp with a capacitor in the feedback path that makes it into a low-pass filter. This filter averages the phase detector pulses into a constant dc voltage that biases the VCO varactors. The average dc voltage is proportional to the duty cycle, which is the ratio of the binary 1 pulse time to the period of the signal. Narrow pulses (low duty cycle) produce a low average dc voltage, and wide pulses (high duty cycle) produce a high average dc voltage. Fig. 8-11(e) shows how the average dc voltage varies with phase shift. Most PLLs lock in at a phase difference of 90°. Then, as the frequency of the VCO changes because of drift or because of changes in the frequency divider ratio, the input to the phase detector from
the feedback divider changes, varying the duty cycle. This changes the dc voltage from the loop filter and forces a change of the VCO frequency to compensate for the original change. Note that the XOR produces a positive dc average voltage, but the op amp used in the loop filter inverts this to a negative dc voltage, as required by the VCO.
The output frequency of the synthesizer fo and the phase detector reference frequency fr are related to the overall divider ratio R as follows:
In our example, the reference input to the phase detector fr must be 30 kHz to match the feedback from the VCO output fo. Assume a VCO output frequency of 389.76 MHz. A frequency divider reduces this amount to 30 kHz. The overall division ratio is R = fo /fr = 389,760,000/30,000 = 12,992.
In some very high-frequency PLL synthesizers, a special frequency divider called a prescaler is used between the high-output frequency of the VCO and the programmable part of the divider. The prescaler could be one or more emitter- coupled logic (ECL) flipflops or a low-ratio CMOS frequency divider that can operate at frequencies up to 1 to 2 GHz. Refer again to Fig. 8-9. The prescaler divides by a ratio of M = 64 to reduce the 389.76-MHz output of the VCO to 6.09 MHz, which is well within the range of most programmable frequency dividers. Since we need an overall division ratio of R = 12,992 and a factor of M = 64 is in the prescaler, the programmable portion of the feedback divider N can be computed. The total division factor is R = MN = 12,992. Rearranging,
we have N = R/M = 12,992/64 = 203.
Now, to see how the synthesizer changes output frequencies when the division ratio is changed, assume that the programmable part of the divider is changed by one increment, to N = 204. For the PLL to remain in a locked state, the phase detector input must remain at 30 kHz. This means that the VCO output frequency must change. The new frequency division ratio is 204 x 64 = 13,056. Multiplying this by 30 kHz yields the new VCO output frequency fo = 30,000 x 13,056 =391,680,000 Hz = 391.68 MHz. Instead of the desired 30-kHz increment, the VCO output varied by 391,680,000 – 389,760,000 = 1,920,000 Hz, or a step of 1.92 MHz. This was caused by the prescaler. For a 30-kHz step to be achieved, the feedback divider should have changed its ratio from 12,992 to 12,993. Since the prescaler is fixed with a division factor of 64, the smallest increment step is 64 times the reference frequency, or 64 x 30,000 = 1,920,000 Hz. The prescaler solves the problem of having a divider with a high enough frequency capability to handle the VCO output, but forces the use of programmable dividers for only a portion of the total divider ratio. Because of the prescaler, the divider ratio is not stepped in integer increments but in increments of 64. Circuit designers can either live with this or find another solution.
One possible solution is to reduce the reference frequency by a factor of 64. In the example, the reference frequency would become 30 kHz/64 – 468.75 Hz. To achieve this frequency at the other input of the phase detector, an additional division factor of 64 must be included in the programmable divider, making it N = 203 x 64 = 12,992. Assuming the original output frequency of 389.76 MHz, the overall divider ratio is R = MN = 12,992(64) = 831,488. This makes the output of the programmable divider equal to the reference frequency, or fr = 389,760,000/831,488 = 468.75 Hz.
This solution is logical, but it has several disadvantages. First, it increases cost and complexity by requiring two more divide-by-64 ICs in the reference and feedback paths. Second, the lower the operating frequency of the phase detector, the more difficult it is to filter the output into direct current. Further, the low-frequency response of the filter slows the process of achieving lock. When a change in the divider ratio is made, the VCO frequency must change. It takes a finite amount of time for the filter to develop the necessary value of the corrective voltage to shift the VCO frequency. The lower the phase detector frequency, the greater this lock delay time. It has been determined that the lowest acceptable frequency is about 1 kHz, and even this is too low in some applications. At 1 kHz, the change in VCO frequency is very slow as the filter capacitor changes its charge in response to the different duty-cycle pulses of the phase detector. With a 468.75-Hz phase detector frequency, the loop response becomes even slower. For more rapid frequency changes, a much higher frequency must be used. For spread spectrum and in some satellite applications, the frequency must change in a few microseconds or less, requiring an extremely high reference frequency.
To solve this problem, designers of high-frequency PLL synthesizers created special IC frequency dividers, such as the one diagrammed in Fig. 8-12. This is known as a fractional N divider PLL. The VCO output is applied to a special variable-modulus pre scaler divider. It is made of emitter-coupled logic or CMOS circuits. It is designed to have two divider ratios, M and M + 1. Some commonly available ratio pairs are 10/11, 64/65, and 128/129. Let’s assume the use of a 64/65 counter. The actual divider ratio is determined by the modulus control input. If this input is binary 0, the prescaler divides by M, or 64; if this input is binary 1, the prescaler divides by M + 1, or 65. As Fig. 8-12 shows, the modulus control receives its input from an output of counter A. Counters A and N are programmable down-counters used as frequency dividers. The divider ratios are preset into the counters each time a full divider cycle is achieved. These ratios are such that N . A. The count input to each counter comes from the output of the variable-modulus prescaler.
A divider cycle begins by presetting the down-counters to A and N and setting the Prescaler to M+ 1 = 65. The input frequency from the VCO is fo. The input to the down-counters is fo/65. Both counters begin down-counting. Since A is a shorter counter than N, A will decrement to 0 first. When it does, its detect-0 output goes high, changing the modulus of the Prescaler from 65 to 64. The N counter initially counts down by a factor of A but continues to down-count with an input of fo /64. When it reaches 0, both down-counters are preset again, the dual modulo Prescaler is changed back to a divider ratio of 65, and the cycle starts over.
The total division ratio R of the complete divider in Fig. 8-12 is R = MN + A. If M = 64, N = 203, and A = 8, the total divider ratio is R = 64(203) + 8 = 12,992 + 8 = 13,000. The output frequency is fo = Rfr = 13,000(30,000) = 390,000,000 = 390 MHz.
Any divider ratio in the desired range can be obtained by selecting the appropriate preset values for A and N. Further, this divider steps the divider ratio one integer at a time so that the step increment in the output frequency is 30 kHz, as desired.
As an example, assume that N is set to 207 and A is set to 51. The total divider ratio is R = MN = A = 64(207) + 51 + 13,248 + 51 = 13,299. The new output frequency is fo = 13,299(30,000) =398,970,000 = 398.97 MHz.
If the A value is changed by 1, raising it to 52, the new divide ratio is R = MN + A= 64(207) + 52 = 13,248 + 52 = 13,300. The new frequency is fo = 13,300(3,000) =399,000,000 = 399 MHz. Note that with an increment change in A of 1, R changed by 1 and the final output frequency increased by a 30-kHz (0.03-MHz) increment, from 398.97 to 399 MHz.
The preset values for N and A can be supplied by almost any parallel digital source but are usually supplied by a microprocessor or are stored in a ROM. Although this type of circuit is complex, it achieves the desired results of stepping the output frequency in increments equal to the reference input to the phase detector and allowing the reference frequency to remain high so that the change delay in the output frequency is shorter.
A frequency synthesizer has a crystal reference oscillator of 10 MHz followed by a divider with a factor of 100. The variable-modulus Prescaler has M = 31/32. The A and N down-counters have factors of 63 and 285, respectively. What is the synthesizer output frequency?
The reference input signal to the phase detector is
10 MHz/100 = 0.1 MHz = 100 kHz
The total divider factor R is
R 5=MN + A = 32 (285) + 63 = 9183
The output of this divider must be 100 kHz to match the 100-kHz reference signal to achieve lock. Therefore, the input to the divider, the output of the VCO, is R times 100 kHz, or
fo = 9183 (0.1 MHz) = 918.3 MHz
Demonstrate that the step change in output frequency for the synthesizer in Example 8.3 is equal to the phase detector reference range, or 0.1 MHz. Changing the A factor one increment to 64 and recalculating the output yield
R = 32(285) + 64 = 9184
fo = 9184(0.1 MHz) = 918.4 MHz
The increment is 918.4 – 918.3 = 0.1 MHz.
Direct Digital Synthesis
A newer form of frequency synthesis is known as direct digital synthesis (DDS). A DDS synthesizer generates a sine wave output digitally. The output frequency can be varied in increments depending upon a binary value supplied to the unit by a counter, a register, or an embedded microcontroller.
The basic concept of the DDS synthesizer is illustrated in Fig. 8-13. A read-only memory (ROM) is programmed with the binary representation of a sine wave. These are the values that would be generated by an analog-to-digital (A/D) converter if an analog sine wave were digitized and stored in the memory. If these binary values are fed to a digital-to-analog (D/A) converter, the output of the D/A converter will be a stepped approximation of the sine wave. A low-pass filter (LPF) is used to remove the high frequency content near the clock frequency, thereby smoothing the ac output into a nearly perfect sine wave.
To operate this circuit, a binary counter is used to supply the address word to the ROM. A clock signal steps the counter that supplies a sequentially increasing address to ROM. The binary numbers stored in ROM are applied to the D/A converter, and the stepped sine wave is generated. The frequency of the clock determines the frequency of the sine wave.
To illustrate this concept, assume a 16-word ROM in which each storage location has a 4-bit address. The addresses are supplied by a 4-bit binary counter that counts from 0000 through 1111 and recycles. Stored in ROM are binary numbers representing values that are the sine of particular angles of the sine wave to be generated. Since a sine wave is 360° in length, and since the 4-bit counter produces 16 addresses or increments, the binary values represent the sine values at 360/16 = 22.5° increments.
Assume further that these sine values are represented with 8 bits of precision. The 8-bit binary sine values are fed to the D/A converter, where they are converted to a proportional voltage. If the D/A converter is a simple unit capable of a dc output voltage only, it cannot produce a negative value of voltage as required by a sine wave. Therefore, we will add to the sine value stored in ROM an offset value that will produce a sine wave output, but shifted so that it is all positive. For example, if we wish to produce a sine wave with a 1-V peak value, the sine wave would vary from 0 to +1, then back to 0, from 0 to -1, and then back to 0, as shown in Fig. 8-14(a). We add a binary 1 to the waveform so that the output of the D/A converter will appear as shown in Fig. 8-14(b). The D/A converter output will be 0 at the peak negative value of the sine wave. This value of 1 is added to each of the sine values stored in ROM. Fig. 8-15 shows the ROM address, the phase angle, sine value, and the sine value plus 1.
If the counter starts counting at zero, the sine values will be sequentially accessed from ROM and fed to the D/A converter, which produces a stepped approximation of the sine wave. The resulting waveform (red) for one complete count of the counter is shown in Fig. 8-16. If the clock continues to count, the counter will recycle and the sine wave output cycle will be repeated.
An important point to note is that this frequency synthesizer produces one complete sine wave cycle for every 16 clock pulses. The reason for this is that we used 16 sine values to create the one cycle of the sine wave in ROM.
To get a more accurate representation of the sine wave, we could have used more bits. For example, if we had used an 8-bit counter with 256 states, the sine values would be spaced every 360/256 = 1.4°, giving a highly accurate representation of the sine wave. Because of this relationship, the output frequency of the sine wave f0 = the clock frequency fclk/2n, where N is equal to the number of address bits in ROM.
If a clock frequency of 1 MHz were used with our 4-bit counter, the sine wave output frequency would be
f0 = 1,000,000/24 = 1,000,000/16 = 62,500 Hz
The stepped approximation of the sine wave is then applied to a low-pass filter where the high-frequency components are removed, leaving a low-distortion sine wave.
The only way to change the frequency in this synthesizer is to change the clock frequency. This arrangement does not make much sense in view of the fact that we want our synthesizer output to have crystal oscillator precision and stability. To achieve this, the clock oscillator must be crystal-controlled. The question then becomes, How can you modify this circuit to maintain a constant clock frequency and also change the frequency digitally?
The most commonly used method to vary the synthesizer output frequency is to replace the counter with a register whose content will be used as the ROM address but also one that can be readily changed. For example, it could be loaded with an address from an external microcontroller. However, in most DDS circuits, this register is used in conjunction with a binary adder, as shown in Fig. 8-17. The output of the address register is applied to the adder along with a constant binary input value. This constant value can also be changed. The output of the adder is fed back into the register. The combination of the register and adder is generally referred to as an accumulator. This circuit is arranged so that upon the occurrence of each clock pulse, the constant C is added to the
previous value of the register content and the sum is re-stored in the address register. The constant value comes from the phase increment register, which in turn gets it from an embedded microcontroller or other source.
To show how this circuit works, assume that we are using a 4-bit accumulator register and the same ROM described previously. Assume also that we will set the constant value to 1. For this reason, each time a clock pulse occurs, a 1 is added to the content of the register. With the register initially set to 0000, the first clock pulse will cause the register to increment to 1. On the next clock pulse the register will increment to 2, and so on. As a result, this arrangement acts just as the binary counter described earlier.
Now assume that the constant value is 2. This means that for each clock pulse, the register value will be incremented by 2. Starting at 0000, the register contents would be 0, 2, 4, 6, and so on. Looking at the sine value table in Fig. 8-15, you can see that the values output to the D/A converter also describe the sine wave, but the sine wave is being generated at a more rapid rate. Instead of having eight amplitude values represent the peak-to-peak value of the sine wave, only four values are used. Refer to Fig. 8-16, which illustrates what the output looks like (blue curve). The output is, of course, a stepped approximation of a sine wave, but during the complete cycle of the counter from 0000 through 1111, two cycles of the output sine wave occur. The output has fewer steps and
is a cruder representation. With an adequate low-pass filter, the output will be a sine wave whose frequency is twice that generated by the circuit with a constant input of 1.
The frequency of the sine wave can further be adjusted by changing the constant value added to the accumulator. Setting the constant to 3 will produce an output frequency that is three times that produced by the original circuit. A constant value of 4 produces a frequency four times the original frequency.
With this arrangement, we can now express the output sine wave frequency with the formula
The higher the constant value C, the fewer the samples used to reconstruct the output sine wave. When the constant is set to 4, every fourth value in Fig. 8-15 will be sent to the D/A converter, generating the dashed waveform in Fig. 8-16. Its frequency is four times the original. This corresponds to two samples per cycle, which is the least number that can be used and still generate an accurate output frequency. Recall the Nyquist criterion, which says that to adequately reproduce a sine wave, it must be sampled a minimum of two times per cycle to reproduce it accurately in a D/A converter.
to make the DDS effective, then, the total number of sine samples stored in ROM must be a very large value. Practical circuits use a minimum of 12 address bits, giving 4096 sine samples. Even a larger number of samples can be used.
The DDS synthesizer described earlier offers some advantages over a PLL synthesizer. First, if a sufficient number of bits of resolution in ROM word size and the accumulator size are provided, the frequency can be varied in very fi ne increments. And because the clock is crystal-controlled, the resulting sine wave output will have the accuracy and precision of the crystal clock.
A second benefit is that the frequency of the DDS synthesizer can usually be changed much faster than that of a PLL synthesizer. Remember that to change the PLL synthesizer frequency, a new frequency-division factor must be entered into the frequency divider. Once this is done, it takes a finite amount of time for the feedback loop to detect the error and settle into the new locked condition. The storage time of the loop low-pass filter considerably delays the frequency change. This is not a problem in the DDS synthesizer, which can change frequencies within nanoseconds.
A downside of the DDS synthesizer is that it is difficult to make one with very high output frequencies. The output frequency is limited by the speed of the available D/A converter and digital logic circuitry. With today’s components, it is possible to produce a DDS synthesizer with an output frequency as high as 200 MHz. Further developments in IC technology will increase that in the future. For applications requiring higher frequencies, the PLL is still the best alternative.
DDS synthesizers are available from several IC companies. The entire DDS circuitry is contained on a chip. The clock circuit is usually contained within the chip, and its frequency is set by an external crystal. Parallel binary input lines are provided to set the constant value required to change the frequency. A 12-bit D/A converter is typical. An example of such a chip is the Analog Devices AD9852, shown in Fig. 8-18. The on-chip clock is derived from a PLL used as a frequency multiplier that can be set to multiply by any integer value between 4 and 20. With a maximum of 20, a clock frequency of 300 MHz is generated. To achieve this frequency, the external reference clock input must be 300/20 = 15 MHz. With a 300-MHz clock, the synthesizer can generate sine waves up to 150 MHz.
The outputs come from two 12-bit DACs that produce both the sine and the cosine waves simultaneously. A 48-bit frequency word is used to step the frequency in 248 increments. A 17-bit phase accumulator lets you shift the phase in 217 increments.
A 17-bit phase accumulator lets you shift the phase in 217 increments. This chip also has circuitry that lets you modulate the sine wave outputs. AM, FM, FSK, PM, and BPSK can be implemented. More advanced DDS ICs are available with DAC resolution to 14-bits and a maximum clock input of 1 GHz.
Keep one important thing in mind. Although there are individual PLL and DDS synthesizer chips, today these circuits are more likely to be part of a larger system on a chip (SoC).
An important specification and characteristic of any signal (carrier) source, crystal oscillator, or frequency synthesizer is phase noise. Phase noise is the minor variation in the amplitude and phase of the signal generator output. The noise comes from natural semiconductor sources, power supply variations, or thermal agitation in the components. The phase variations manifest themselves as frequency variations. The result is what appears to be a sine wave signal source that has been amplitude and frequency modulated. Although these variations are small, they can result in degraded signals in both the transmitter and the receiver circuits.
For example, in the transmitter, variations in the carrier other than those imposed by the modulator can produce a “fuzzy” signal that can result in transmission errors. In the receiver, any added noise can mask and interfere with any small signals being received. A particularly difficult problem is the multiplication of the phase noise in PLL synthesizers. A PLL is a natural frequency multiplier that in effect amplifies the phase noise of the input crystal oscillator. The goal, therefore, is to minimize phase noise in the carrier signal by design or through the selection of signal sources with the least phase noise.
When looking at a sine wave carrier on a spectrum analyzer, what you should see is a single vertical straight line, its amplitude representing the signal power and its horizontal position representing the carrier frequency (fc).
See Fig. 8-19a. However, because of signal distortion or noise, what you actually see is the carrier signal accompanied by sidebands around the carrier made up of harmonics and phase noise components. Fig. 8-19b is an example. Serious harmonic distortion can be filtered out, but the phase noise cannot.
Notice in Fig. 8-19b that the noise sidebands occur both above and below the carrier frequency. When measuring phase noise, only the upper sidebands are considered; it is assumed that, because of the random nature of the noise, both upper and lower sidebands will be identical. Phase noise is designated as L(f) and represents the single-sideband power referenced to the carrier. It is calculated and measured as the ratio of the average noise power (Pn) in a 1 Hz bandwidth at a point offset from the carrier to the carrier signal power (Pc) expressed in dBc/Hz. The average noise power is referred to as the spectral power density,
L(f) = Pn /Pc
Fig. 8-20 shows a plot of the phase noise. Note that the noise power is averaged over a narrow 1-Hz bandwidth. The location of that 1-Hz window is offset from the carrier.
The phase noise is measured at different offset values from 1 kHz to 10 MHz or more, depending on the frequencies involved, the modulation type, and the application. Close-in phase noise is in the 1-kHz to 10-kHz range, whereas far-out phase noise is offset by 1 MHz or more.
The range of common phase noise values is −40 dBc/Hz to −170 dB/Hz. The greater the number, of course, the lower the phase noise. The noise floor is the lowest possible level and is defined by the thermal power in the circuitry and could be as low as −180 dBc/Hz. In Fig. 8-20 the phase noise is −120 dBc/Hz at 100 kHz.
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reference : Electronic communication by Louis Frenzel, book