VHF Aircraft Communication Circuit
Receiver:- Most modern receivers are in IC form. Virtually all of the circuitry can be incorporated in a single chip. Some external discrete components are still needed but are minimal. These may include coils, bypass, and tuning capacitors, antennas, crystals, filters, and in the case of audio, a power amplifier, and speaker or headphones.
Some discrete designs still exist and are good examples of overall receiver architecture. The example to follow is a VHF receiver for aircraft radio.
The typical VHF receiver circuit shown in Fig. 9-36 is designed to receive two-way aircraft communication between planes and airport controllers, which takes place in the VHF range of 118 to 135 MHz. Amplitude modulation is used. Like most modern receivers, the circuit is a combination of discrete components and ICs.
The signal is picked up by an antenna and fed through a transmission line to input jack J1. The signal is coupled through C1 to a tuned filter consisting of the series and parallel-tuned circuits made up of L1–L5 and C2–C6. This broad bandpass filter passes the entire 118- to 135-MHz range.
The output of the filter is connected to an RF amplifier through C7, which is made up of transistor Q1 and its bias resistor R4 and collector load R5. The signal is then applied to the NE602 IC, U1–C8, which contains a balanced mixer and a local oscillator. The local oscillator frequency is set by the circuit made up of inductor L6 and the related components. And C14 and D1 in parallel form the capacitor that resonates with L6 to set the frequency of the local oscillator. Tuning of the oscillator is accomplished by varying the dc bias on a varactor D1. Potentiometer R1 sets the reverse bias, which in turn varies the capacitance to tune the oscillator.
A superheterodyne receiver is tuned by varying the local oscillator frequency, which is set to a frequency above the incoming signal by the amount of the IF. In this receiver, the IF is 10.7 MHz, a standard value for many VHF receivers. To tune the 118- to 135-MHz range, the local oscillator is varied from 128.7 to 145.7 MHz.
The output of the mixer, which is the difference between the incoming signal frequency and the local oscillator frequency, appears at pin 4 of the NE602 and is fed to a ceramic bandpass filter set to the IF of 10.7 MHz. This filter provides most of the receiver’s selectivity. The insertion loss of the filter is made up by an amplifier made of Q2, its bias resistor R10, and collector load R11. The output of this amplifier drives an MC1350 IC through C16. An integrated IF amplifier, U2 provides extra gain and selectivity. The selectivity comes from the tuned circuit made up of IF transformer T1. The MC1350 also contains all the AGC circuitry.
The signal at the secondary of T1 is then fed to a simple AM diode detector consisting of D2, R12, and C30. The demodulated audio signal appears across R12 and is then fed to op-amp U3b, a noninverting circuit biased by R13 and R14 that provides extra amplification for the demodulated audio and the average direct current at the detector output. This amplifier feeds the volume control, potentiometer R2. The audio signal goes from there through C25 and R24 to another op-amp, U3c. Here the signal is further amplified and fed to the 386 IC power amplifier U4. This circuit drives the speaker, which is connected via jack J2.
The audio signal from the diode detector contains the dc level resulting from detection (rectification). Both the audio and the direct current are amplified by U3b and further filtered into a nearly pure direct current by the low-pass filter made of R15 and C22. This dc signal is applied to op-amp U3a, where it is amplified into a dc control voltage. This direct current at the output pin 1 of U3 is fed back to pin 5 on the MC1350 IC to provide AGC control ensuring a constant comfortable listening level despite wide variations in signal strength.
The AGC voltage from U3a is also fed to an op-amp comparator circuit made from amplifier U3d. The other input to this comparator is a dc voltage from potentiometer R3, which is used as a squelch control. Since the AGC voltage from U3a is directly proportional to the signal strength, it is used as the basis for setting the squelch to a level that will blank the receiver until a signal of a predetermined strength comes along.
If the signal strength is very low or no signal is tuned in, the AGC voltage will be very low or nonexistent. This causes D3 to conduct, effectively disabling amplifier U3c and preventing the audio signal from the volume control from passing through to the power amplifier. If a strong signal exists, D3 will be reverse-biased and thus will not interfere with amplifier U3c. As a result, the signal from the volume control passes to the power amplifier and is heard in the speaker.
IC AM / FM / SW Radio
A good example of a modern IC receiver is the Silicon Laboratories Si473x-D60. It is designed to implement standard AM and FM analog radios as well as shortwave (SW) and long-wave (LW) radios. It is made of silicon CMOS and contains all of the necessary circuitry except for that needed for the audio output. It is housed in a 20-pin surface-mount plastic package that measures 3 mm x 3 mm.
A block diagram of this receiver is given in Fig. 9-37. It is essentially two receivers, one for AM and SW and the other for FM. The AM receiver covers the 520 to 1710 kHz range. The FM receiver covers the 64 to 108 MHz range. The shortwave coverage extends from 2.3 to 26.1 MHz.
The long-wave coverage is from 153 to 279 kHz. The chip operates from a dc power source in the 2.7 to 5.5-volt range. The dc is applied to the VA pin along with an external bypass capacitor. This voltage is regulated by an internal low drop out (LDO) regulator. A separate digital and I/O supply of 1.62 to 3.6 volts is needed at pin VD.
A low-noise amplifier (LNA) amplifies the signal input from an antenna connected to the FMI pin. AGC is used to control the gain. The signal is then sent to a pair of mixers connected as an image-reject mixer that down-converts the incoming RF down to a low IF of 125 kHz. The local oscillator is an on-chip PLL synthesizer. The synthesizer uses automatic frequency control (AFC) and is locked to an external 32.768-kHz reference clock (RCLK). A 32.768-kHz crystal is external to the chip. FM tuning is in 10-kHz steps.
A pair of multiplexers (Mux) selects the FM I and Q signals from the mixers and sends them to a pair of analog to digital converters (ADC). The ADC outputs go to a digital signal processor (DSP) where the low IF filtering, demodulation, de-emphasis, stereo processing, and other operations take place. The digital outputs go to digital-to-analog converters (DAC) that reproduce the analog stereo left and right audio output signals at ROUT and LOUT pins. This chip can also output serial digital audio signals (DOUT) in a variety of formats similar to CD audio. The digital audio section may be formatted for 8, 16, 20, or 24 bits at standard sampling rates of 32 kHz, 44.1 kHz, or 48 kHz.
The AM/SW/LW receiver is similar, with input from a loop antenna at pin AMI to an LNA and image-reject mixer. The multiplexers send the mixer I and Q outputs to the ADCs and then to the DSP, where demodulation occurs. AM, SW, and LW tuning is in 1-kHz steps. The tuning for both receivers is accomplished digitally by an external.
microcontroller by way of the on-chip control interface. The interface signals use the I2C bus with its SCLK and SDIO signals. Another feature of the chip is the inclusion of a Radio Data System (RDS) circuit that allows broadcast stations to send station identification, song titles, and other information to a display on the receiver.
SDR Communications Receiver
Software-defined radio (SDR) receivers are becoming the most common form of radio today, either in integrated circuit form or as a completed product. An example of a commercial shortwave/amateur radio receiver using SDR concepts is the SDR-IQ made by RFSPACE Inc. Fig. 9-38 shows the receiver along with an antenna tuner that matches a variety of antenna types to the 50-ohm input to the receiver. The SDR-IQ is designed to be used with a desktop PC or laptop. The receiver is just the front-end, while the PC is used for the DSP and the display. The general frequency range is 500 kHz to 30 MHz. It can demodulate AM, SSB, DSB, FM, and CW (continuous wave or Morse code) signals.
A block diagram of the receiver is shown in Fig. 9-39. Input filters select one of three ranges: 0 to 5 MHz, 5 MHz to 15 MHz, or 15 MHz to 30 MHz. The selected bandwidth of signals is applied to an Analog Devices AD8370 variable gain amplifier (VGA). This amplifier provides the receiver gain selectable digitally in two ranges: -11 dB to +17 dB or +6 dB to 34 dB. The gain is varied digitally to provide AGC.
The VGA output goes to a 40-MHz low-pass filter (LPF), which serves as an antialiasing filter for the ADC. The ADC is an Analog Devices AD9245 digitizer that samples at a rate of 66.6667 MHz, more than twice the upper signal input of 30 MHz. The output consists of 14-bit parallel samples.
The 14-bit samples are sent to an Analog Devices AD6620, a digital signal processor for receivers. It contains digital mixers and a numerically controlled oscillator (NCO) that downconverts the signal to baseband. The NCO is the local oscillator and is similar to the signal generation section of a DDS synthesizer as discussed in Chap. 8. The mixer outputs are the I and Q baseband signals. Circuits called decimators reduce the sampling rate and output the digital I and Q signals to the ARM7 microcontroller. The microcontroller puts the I and Q signals into packets and sends them to the USB (Universal Serial Bus) interface, which then connects to the PC. The microcontroller also operates the filter selection, AGC, and ADC.
The receiver is also fully powered by the 5-volt dc furnished by the USB port connection.
The PC uses its internal Pentium or equivalent processor with the I and Q signals to perform the demodulation. Then a fast Fourier transform (FFT) is performed on the data to provide a frequency domain output. Software on the PC also implements the receiver controls and display. Fig. 9-40 shows the PC video monitor display. The PC mouse and keyboard are used to select the frequency and mode of operation. The upper part of the display (dark background) is the FFT frequency domain display, similar to what you would see on a spectrum analyzer. A 190-kHz segment of the received spectrum is shown. The center signal is that of AM radio station WOAI at 1200 kHz. You can even see the upper and lower sidebands.
The lower part of the display (blue) is called a waterfall display. It shows signal strength by the color level of the signals within the 190-kHz bandwidth of signals displayed. The waterfall display is moving and flows downward slowly over time, emulating a waterfall. The receiver operator, therefore, gets an ongoing display of present and past signal conditions.
In the past, communication equipment was individually packaged in units based on function, and so transmitters and receivers were almost always separate units. Today, most two-way radio communication equipment is packaged so that both transmitter and receiver are in a unit known as a transceiver. Transceivers range from large, high-power desktop units to small, pocket-sized, handheld units. Cell phones are transceivers as are the wireless local-area networking units on PCs.
Transceivers provide many advantages. In addition to having common housing and power supply, the transmitters, and receivers can share circuits, thereby achieving cost savings and, in some cases, smaller size.
Some of the circuits that can perform a dual function are antennas, oscillators, frequency synthesizers, power supplies, tuned circuits, filters, and various kinds of amplifiers. Thanks to modern semiconductor technology, most transceivers are a single silicon chip.
Fig. 9-41 is a general block diagram of a high-frequency transceiver capable of CW and SSB operation. Both the receiver and the transmitter make use of heterodyning techniques for generating the IF and final transmission frequencies, and proper selection of these intermediate frequencies allows the transmitter and receiver to share local oscillators. Local oscillator 1 is the BFO for the receiver product detector and the carrier for the balanced modulator for producing DSB. Later, crystal local oscillator 2 drives the second mixer in the receiver and the first transmitter mixer used for upconversion. Local oscillator 3 supplies the receiver first mixer and the second transmitter mixer.
In transmission mode, the crystal filter (another shared circuit) provides sideband selection after the balanced modulator. In the receive mode, the filter provides selectivity for the IF section of the receiver. Tuned circuits may be shared. A tuned circuit can be the tuned input for the receiver or the tuned output for the transmitter. Circuit switching may be manual but is often done using relays or diode electronic switches. In most newer designs, the transmitter and receiver share a frequency synthesizer.
fig. 9-42 shows a PLL synthesizer for a 40-channel CB transceiver. Using two crystal oscillators for reference and a single-loop PLL, it synthesizes the transmitter frequency and the two local oscillator frequencies for a dual- conversion receiver for all 40 CB channels. The reference crystal oscillator, which operates at 10.24 MHz, is divided by 2 with a flip-flop and then a binary frequency divider that divides by 1024 to produce a 5-kHz frequency (10.24 MHz/2 = 5.12 MHz/1024 = 5 kHz) that is then applied to the phase detector. The channel spacing is, therefore, 5 kHz.
The phase detector drives the low-pass filter and a VCO that generates a signal in the 16.27- to 16.71-MHz range. This is the local oscillator frequency for the first receiver mixer
Assume, e.g., that it is desired to receive on CB channel 1, or 26.965 MHz. The programmable divider is set to the correct ratio to produce a 5-kHz output when the VCO is 16.27. The first receiver mixer produces the difference frequency of 26.965 – 16.27 = 10.695 MHz. This is the first intermediate frequency. The 16.27-MHz VCO signal is also applied to mixer A; the other input to this mixer is 15.36 MHz, which is derived from the 10.24-MHz reference oscillator and a frequency tripler (x3). The output of mixer A drives the programmable divider, which feeds the phase detector. The 10.24-MHz reference output is also used as the local oscillator signal for the second receiver mixer. With a 10.695 first IF, the second IF is, then, the difference, or 10.695 – 10.24 MHz = 0.455 MHz or 455 kHz.
The VCO output is also applied to mixer B along with a 10.695-MHz signal from a second crystal oscillator. The sum output is selected, producing the transmit frequency 10.695 + 16.27 = 26.965 MHz. This signal drives the class C drivers and power amplifiers
Channel selection is achieved by changing the frequency-division ratio on the programmable divider, usually with a rotary switch or a digital keypad that controls a microprocessor. The circuitry in the synthesizer is usually contained on a single IC chip.
IC Wi-Fi Transceiver
Fig. 9-43 shows an integrated transceiver typical of those used in wireless local-area networks (WLANs). The transceiver is built into PCs, laptops, and other devices to wirelessly communicate with another computer and a network. This particular transceiver meets the specifications set by the IEEEs 802.11b standard for WLANs. Also known as Wi-Fi for wireless fidelity, it operates in the industrial- scientific medical (ISM) band of 2.4 to 2.483 GHz. It is made entirely of silicon CMOS and
BiCMOS and contains most of the circuitry needed to form a complete two-way radio for transmitting and receiving digital data. The device which is housed in a tiny 7 x 7 mm package is accompanied by two other ICs, the power amplifier (PA) for the transmitter, and a baseband processor plus the support circuits such as the A/D and D/A converters.
The transceiver can transmit at a speed of up to 11 Mb/s but can also transmit at lower rates of 5.5, 2, and 1 Mb/s depending upon the noise level, range, and operating environment. The modulation is some form of phase-shift keying. The maximum range is about 100 m, although that varies with the conditions of operation. The speed of transmission is adjusted automatically depending upon the environmental situation. All these operations are handled automatically by the external processor.
The antenna feeds a bidirectional filter such as a SAW filter to provide some selectivity in both transmit and receive operations. The filter output is fed to a transmit/receive switch (T/R) that is implemented with GaAs transistors or PIN diodes and provides automatic switchover from send to receive. A balun external to the chip provides some impedance matching to the receiver input. The upper part of the transceiver chip is the receiver. The first stage is a low-noise variable-gain amplifier (VGA). This amplifier drives a pair of mixers that are also fed with local oscillator signals that are 90° out of phase. Since this is a zero-IF (ZIF) radio, the local oscillator (LO) signal is at the operating frequency. This LO signal is derived from an internal PLL frequency synthesizer. The reference crystal oscillator and loop filter capacitor are off-chip. The I and Q signals generated by the mixers are filtered by on-chip active low-pass RC filters and amplified by variable-gain amplifiers. The amplified I and Q signals are sent to analog-to-digital converters (ADCs) whose outputs feed the baseband processor where demodulation and other operations are performed on the received data.
There are several other features of the receiver to consider. First, note that all transmission lines between circuits are two-wire. This means that the signals are balanced to ground and sent and received differentially. This arrangement helps minimize noise. Second, note that a digital output from the baseband processor feeds a DAC whose output is used to control the gain of the variable gain amplifiers. This is a form of AGC. Third, note that the frequency synthesizer is controlled by a serial input signal from the baseband processor. The operating channel is selected by the processor, and a serial control world is generated and sent via the serial interface to the programming interface which sets the synthesizer frequency of operation.
The transmitter is located at the bottom of the chip diagram in Fig. 9-43. Binary signals representing the modulated data to be transmitted are developed by the processor and sent to DACs in an I and Q configuration. The signals are all differential. The DAC output feed amplifiers and filters in the transceiver chip where they are sent to two I and Q mixers. Here the baseband signals are up-converted to the final transmit frequency. The on-chip synthesizer generates the carrier frequency for the mixers while a phase shifter produces the quadrature signals. The mixer output are added and then fed to a low-power amplifier with variable gain.
This amplifier feeds an external balun that provides a match to the power amplifier (PA). The power amplifier is a class AB power amplifier with an output power of 2 dBm. The power amplifier is a separate chip and not integrated onto the transceiver chip because it generates too much heat and requires a separate package. The power amplifier output is fed to the transmit/receive switch and then the antenna via the filter.
Note that the PA has a power monitoring detector whose output is digitized by a separate ADC, and this output is used in a feedback scheme to control the transmitter power. The processor computes the desired power and sends a binary signal to a DAC that, in turn, drives the variable-gain amplifier at the transceiver output. Various mode control registers and circuits are also provided to implement the various operations dictated by the standard. Today, the Wi-Fi transceivers are even more complex, as they implement the newer IEEE 802.11a/g/n/ac standards. However, the basic structure and components are the same as those discussed here.
Fig. 9-44 shows a transceiver IC designed for cellular base stations or other wireless equipment. It is actually two transceivers in one chip so that the base station can implement the multiple-input multiple-output (MIMO) feature. MIMO is a technique of using two or more antennas, transmitters, and receivers operating on the same frequency to minimize signal-fading effects for more reliable operation and to multiply the digital data speed. MIMO will be explained.
This Analog Devices AD9361 transceiver chip has an operating frequency range of 70 MHz to 6 GHz. The channel bandwidth can be set anywhere in the range of 200 kHz to 56 MHz. The upper segment of Fig. 9-44 represents the two receivers (RX). Three LNAs amplify the input signals from the external filters. The receiver noise figure is 2 dB at 800 MHz. The signals are next down-converted to baseband by mixers, then amplified with AGC and filtered.
An internal PLL fractional-N synthesizer provides the LO signal for tuning. The signals are then digitized in 12-bit ADCs and the parallel I and Q signals are sent to the data interface where they will go to a DSP for demodulation and other processing.
The dual transmitters (TX) are shown in the lower part of Fig. 9-44. The parallel digital I and Q data with modulation comes into the data interface and is applied to 12-bit DACs, then filtered and amplified. Mixers then up-convert the signals to the final output frequency. A separate PLL synthesizer is used as the TX local oscillator. The maximum RF power output is 7.5 dBm depending on the operating frequency. An external PA is used to boost the signal level to the desired power.
The PLL synthesizer frequencies are set by an external digital programming word that comes in via a serial interface. Other features and functions of the chip are also programmed this way with data from an external microcontroller.
An Important Final Consideration
Keep in mind one important thing. Modern communications equipment is implemented with ICs like those discussed here. The greatest detail that you will ever see is a block diagram and a set of specifications. You never really see the exact circuitry, which in most cases is proprietary to the manufacturer. While some discrete component schematic diagrams are shown in this and other chapters, they are shown as examples and for general background and do not imply that they are used inside ICs. You should concentrate on the functions and specifications of the IC and not specific circuit operations or other internal details. It does not matter what the circuit is, whether you are a design engineer or a maintenance technician. What matters is performance and function. All you need to worry about are input and output signal levels and dc power levels.
IF Amplifiers | RF Input Amplifiers | Squelch Circuits | Controlling Gain ( Receivers and Transceivers | AM / FM / SW Radio | SDR | Wi-Fi )
Digital to Analog Converters | Analog to Digital Converters ( Receivers and Transceivers | AM / FM / SW Radio | SDR | Wi-Fi )
Noise Level & Types | Conversion Receivers | Signal-to-Noise Ratio (SNR) ( Receivers and Transceivers | AM / FM / SW Radio | SDR | Wi-Fi )
Signal Reproduction | Super heterodyne | RF Amplifiers | Mixing ( Receivers and Transceivers | AM / FM / SW Radio | SDR | Wi-Fi )
Impedance Matching Networks | T and π | Transformers and Baluns ( Receivers and Transceivers | AM / FM / SW Radio | SDR | Wi-Fi )
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Reference : Electronic communication by Louis Frenzel