**Converters**: There are many ways to convert digital codes to proportional analog voltages. However, the most popular methods are the R-2R, string, and weighted current source converters. These are available in integrated-circuit form and are also integrated into other larger systems on a chip (SoC).

Table of Contents

**R-2R Converter**

The R-2R converter consists of four major sections, as shown in Fig. 7-14 and described in the next paragraphs.

**Reference Regulators**

The precise reference voltage regulator, a zener diode, receives the dc supply voltage as an input and translates it to a highly precise reference voltage. This voltage is passed through a resistor that establishes the maximum input current to the resistor network and sets the precision of the circuit. The current is called the full-scale current, or IFS:

**Example 7-2** 1. A signal of 15 MHz is sampled at a rate of 28 MHz. What alias is generated?

2. A signal of 140 MHz has a bandwidth of 620 MHz. What is the Nyquist sampling rate?

3. What is the aliased spectrum if the 140 MHz signal is sampled at a rate 60 MHz?

4. What is the desired sampling rate for centering the spectrum in the first Nyquist zone?

where VR = reference voltage, RR = reference resistor

**Resistor Networks**

The precision resistor network is connected in a unique configuration. The voltage from the reference is applied to this resistor network, which converts the reference voltage to a current proportional to the binary input. The output of the resistor network is a current that is directly proportional to the binary input value and the full-scale reference current. Its maximum value is computed as follows:

For an 8-bit D/A converter, N = 8.

Some modern D/A converters use a capacitor network instead of the resistor network to perform the conversion from a binary number to a proportional current.

**Output Amplifiers**

The proportional current is then converted by an op amp to a proportional voltage. The output of the resistive network is connected to the summing junction of the op amp. The output voltage of the op amp is equal to the output current of the resistor network multiplied by the feedback resistor value. If the appropriate value of feedback resistance is selected, the output voltage can be scaled to any desired value. The op amp inverts the polarity of the signal:

VO = – IoRf

**Electronic Switches**

The resistor network is modified by a set of electronic switches that can be either current or voltage switches and are usually implemented with diodes or transistors. These switches are controlled by the parallel binary input bits from a counter, a register, or a microcomputer output port. The switches turn on or off to configure the resistor network. All the components shown in Fig. 7-14 are usually integrated onto a single IC chip. The only exception may be the amp, which may be an external circuit. D/A converters of this type are available in a variety of configurations and can convert 8-, 10-, 12-, 14-, and 16-bit binary words.

The implementation of D/A converter circuitry varies widely. One of the most popular configurations is shown in detail in Fig. 7-15. Only 4 bits is shown, to simplify the drawing. Of particular interest is the resistor network, which uses only two values of resistance and thus is known as an R-2R ladder network. More complex networks have been devised but use a wider range of resistor values that are difficult to make with precise values in IC form. In Fig. 7-15 the switches are shown as mechanical devices, whereas in reality they are transistor switches controlled by the binary input. Many newer D/A converters and A/D converters use a capacitive network instead of the R-2R network.

**String DAC**

The string DAC gets its name from the fact that it is made up of a series string of equal-value resistors forming a voltage divider. See Fig. 7-16. This voltage divider divides the input reference voltage into equal steps of voltage proportional to the binary input. There are 2N resistors in the string, where N is the number of input bits that determines resolution. In Fig. 7-16 the resolution is 23 = 8, so eight resistors are used. Higher resolutions of 10 and 12 bits are available in this configuration. If the input reference is 10 V, the resolution is 10/23 = 10/8 = 1.25 V. The output varies in increments of 1.25 V from 0 to 8.75 V.

The output voltage is determined by a set of enhancement mode MOSFET switches controlled by a standard binary decoder. With 3 bits in, there are eight decoder outputs, each driving one MOSFET switch. If the input code is 000, switch S0 is turned on and the output is ground or 0 V. All other MOSFETs are off at this time. If the input code is 111, then S7 is turned on and the output voltage is 8.75 V. The output is a voltage and may be further conditioned by an op amp with gain and a lower output impedance as needed by the application.

**Weighted Current Source DAC**

A popular configuration for very high-speed DACs is the weighted current source DAC shown in Fig. 7-17. The current sources supply a fixed current that is determined by the external reference voltage. Each current source supplies a binary weighted value of I, I/2, I/4, I/8, etc. The current sources are made up of some combination of resistors, MOSFETs, or in some cases bipolar transistors. The switches are usually fast enhancement mode MOSFETs, but bipolar transistors are used in some models. The parallel binary input is usually stored in an input register, and the register outputs turn the switches off and on as dictated by the binary value. The current source outputs are added at the summing junction of an op amp. The output voltage VO is the sum of the currents It multiplied by the feedback resistor Rf.

VO = ItRf

In Fig. 7-17, with 4 bits of resolution, there are 2N = 24 = 16 increments of current. Assume I = 100 μA. If the input binary number is 0101, then switches S2 and S4 are closed and the current is 50 + 12.5 = 62.5 μA. With a 10-kV feedback resistor, the output voltage would be

62.5 x 1026 x 10 x 103 = 0.625 V.

Current source DACs are used for very fast conversions and are available in resolutions of 8, 10, 12, and 14 bits.

**D/A Converter Specifications**

Four important specifications are associated with D/A converters: speed, resolution, error, and settling time. Speed is the fastest rate that the D/A converter can generate output steps. Modern DACs can achieve rates to 10 Giga samples per second (10 GSPS). Resolution is the smallest increment of voltage that the D/A converter produces over its output voltage range. Resolution is directly related to the number of input bits. It is computed by dividing the reference voltage VR by the number of output steps 2N – 1.

There is 1 fewer increment than the number of binary states. For a 10-V reference and an 8-bit D/A converter the resolution is 10/(28 – 1) = 10/255 = 0.039 V = 39 mV. For high-precision applications, D/A converters with larger input words should be used. D/A converters with 8 and 12 bits are the most common, but D/A converters with 10, 14, 16, 20, and 24 bits are available. Error is expressed as a percentage of the maximum, or full-scale, output voltage, which is the reference voltage value. Typical error figures are less than 60.1 percent.

This error should be less than one-half the minimum increment. The smallest increment of an 8-bit D/A converter with a 10-V reference is 0.039 V, or 39 mV. Expressed as a percentage, this is 0.039 / 10 = 0.0039 x 100 = 0.39 percent. One-half of this is 0.195 percent. With a 10-V reference, this represents a voltage of 0.00195 x 10 = 0.0195 V, or 19.5 mV. A stated error of 0.1 percent of full scale is 0.001 x 10 = 0.01 V, or 10 mV. Settling time is the amount of time it takes for the output voltage of a D/A converter to stabilize to within a specific voltage range after a change in binary input. Refer to Fig. 7-18.

When a binary input change occurs, a finite amount of time is needed for the electronic switches to turn on and off and for any circuit capacitance to charge or discharge. During the change, the output rings and overshoots, and contains transients from the switching action. The output is thus not an accurate representation of the binary input; it is not usable until it settles down. Settling time is the time it takes for the D/A converter’s output to settle to within 61 ⁄2 LSB change. In the case of the 8-bit D/A converter described earlier, when the output voltage settles to less than one-half the minimum voltage change of 39 mV, or 19.5 mV, the output can be considered stable. Typical settling times are in the 100-ns range. This specification is important because it determines the maximum speed of operation of the circuit, called the conversion time.

A 100-ns settling time translates to a frequency of 1/100 x 1029 = 10 MHz. Operations faster than this result in output errors. Monotonicity is another DAC specification. A DAC is monotonic if the output increases in one increment of resolution voltage for each increment of binary number input. In very high-resolution DACs with very small increments, it is possible that circuit inaccuracies could literally result in a decrease in output voltage for a binary increase. This is often caused by poorly trimmed and matched resistors or current sources in the DAC.

Another specification is dc operating voltage and current. Older DACs operated from 15 V, but most of the newer ones operate from 3.3 or 2.5 V. A current consumption figure is also usually given. Another consideration is how many DACs there are per chip. ICs with two, four, and eight DACs per chip are available. In the multi-DAC chips, the binary input is serial. Serial input is an option on most DACs today as the serial input greatly reduces the number of pins devoted to input signals. A 16-bit parallel DAC has, of course, 16 input pins.

The same DAC with a serial input has only one input pin. Typical serial input formats are the serial peripheral interface (SPI) or the I2C interface common on most embedded controllers and microprocessors. The binary input voltage is also a specification. Older DACs used a TTL or CMOS compatible 15 V input while newer chips use lower input signal voltages of 1.8, 2.5, or 3.3 V. High-speed DACs often use current mode logic (CML) inputs or low-voltage differential signaling (LVDS) levels with a differential signal swing of only a few hundred millivolts. The reference voltage is typically from 1 to 5 V from a temperature-compensated zener diode which is usually on the DAC chip.

**A/D Converters**

A/D conversion begins with the process of sampling, which is usually carried out by a sample-and-hold (S/H) circuit. The S/H circuit takes a precise measurement of the analog voltage at specified intervals. The A/D converter (ADC) then converts this instantaneous value of voltage and translates it to a binary number.

**S/H Circuits**

A sample-and-hold (S/H) circuit, also called a track/store circuit, accepts the analog input signal and passes it through, unchanged, during its sampling mode. In the hold mode, the amplifier remembers or memorizes a particular voltage level at the instant of sampling. The output of the S/H amplifier is a fixed dc level whose amplitude is the value at the sampling time. Fig. 7-19 is a simplified drawing of an S/H amplifier.

The main element is a high gain dc differential op amp. The amplifier is connected as a follower with 100 percent feedback. Any signal applied to the non inverting (1) input is passed through unaffected. The amplifier has unity gain and no inversion. A storage capacitor is connected across the very high input impedance of the amplifier. The input signal is applied to the storage capacitor and the amplifier input through a MOSFET gate.

An enhancement mode MOSFET that acts as an on/off switch is normally used. As long as the control signal to the gate of the MOSFET is held high the input signal will be connected to the op amp input and capacitor. When the gate is high, the transistor turns on and acts as a very low-value resistor, connecting the input signal to the amplifier. The charge on the capacitor follows the input signal. This is the sample or track mode for the amplifier. The op amp output is equal to the input.

When the S/H control signal goes low, the transistor is cut off, but the charge on the capacitor remains. The very high input impedance of the amplifier allows the capacitor to retain the charge for a relatively long time. The output of the S/H amplifier, then, is the voltage value of the input signal at the instant of sampling, i.e., the point at which the S/H control pulse switches from high (sample) to low (hold). The op amp output voltage is applied to the A/D converter for conversion to a proportional binary number.

The primary benefit of an S/H amplifier is that it stores the analog voltage during the sampling interval. In some high-frequency signals, the analog voltage may increase or decrease during the sampling interval; this is undesirable because it confuses the A/D converter and introduces what is referred to as aperture error. The S/H amplifier, however, stores the voltage on the capacitor; with the voltage constant during the sampling interval, quantizing is accurate. There are many ways to translate an analog voltage to a binary number. The next sections describe the most common ones.

**Successive-Approximations Converters**

This converter contains an 8-bit successive-approximations register (SAR), as shown in Fig. 7-20. Special logic in the register causes each bit to be turned on one at a time from MSB to LSB until the closest binary value is stored in the register. The clock input signal sets the rate of turning the bits off and on. Assume that the SAR is initially reset to zero.

When the conversion is started, the MSB is turned on, producing 10 000 000 at the output and causing the D/A converter output to go to half-scale. The D/A converter output is applied to the op amp, which applies it to the comparator along with the analog input. If the D/A converter output is greater than the input, the comparator signals the SAR to turn off the MSB. The next MSB is turned on.

The D/A converter output goes to the proportional analog value, which is again compared to the input. If the D/A converter output is still greater than the input, the bit will be turned off; if the D/A converter output is less than the input, the bit will be left at binary 1. The next MSB is then turned on, and another comparison is made. The process continues until all 8 bits have been turned on or off and eight comparisons have been made. The output is a proportional 8-bit binary number. With a clock frequency of 200 kHz, the clock period is 1/200 x 103 = 5 μs. Each bit decision is made during the clock period. For eight comparisons at 5 μs each, the total conversion time is 8 x 5 = 40 μs.

Successive-approximations converters are fast and consistent. They are available with conversion times from about 0.25 to 200 μs, and 8-, 10-, 12-, and 16-bit versions are available. Conversion times are also expressed as mega samples per second (MSPS). Successive-approximations converters with speeds to 5 MSPS are available. Instead of using a D/A converter with an R-2R network, many newer successive approximations converters use capacitors instead of resistors in the weighting network.

The most difficult part of making an integrated-circuit (IC) A/D or D/A converter is the resistor network. It can be made with laser-trimmed thin-fi lm resistors, but these require very expensive processing steps in making the IC. Resistors also take up more space on an IC than any other component. In A/D converters, the R-2R network takes up probably 10 or more times the space of all the rest of the circuitry. To eliminate these problems, a capacitor network can be used to replace the resistor network.

Capacitors are easy to make and take up little space. The basic concept of a capacitive network is shown in Fig. 7-21. This is a simple 3-bit D/A converter. Note that the capacitors have binary weights of C, C/2, and C/4. The total capacitance of all capacitors in parallel is 2C. The actual capacitor values are irrelevant since the capacitor ratios determine the outcome of the conversion. This fact also makes it easy to make the IC, since precise capacitor values are not needed. Only the ratio must be carefully controlled, and this is easier to do when making the IC than with laser trimming resistors.

The switches in this diagram represent MOSFET switches in the actual circuit. A 3-bit successive-approximations register operates the switches labeled S1 through S4. To start the conversion, switches SC and Sin are closed, and switches S1 through S4 connect Vi to the capacitors, which are in parallel at this time. The comparator is shorted out temporarily. The input analog signal to be sampled and converted Vi is applied to all capacitors, causing each to charge up to the current signal value. Next, the SC and Sin switches are opened, storing the current value of the signal on the capacitors. Since the capacitors store the input value at sampling time, no separate S/H circuit is needed. The successive-approximations register and related circuitry switch the reference voltage VREF to the various capacitors in a specific sequence, and the comparator looks at the resulting voltage at each step and makes a decision about whether a 0 or 1 results from the comparison at each step.

For example, in the fi rst step S1 connects VREF to capacitor C, and all other capacitors are switched to ground via S2 to S4. Capacitor C forms a voltage divider with all the other capacitors in parallel. The comparator looks at the junction of the capacitors (node A) and then outputs a 0 or 1 depending upon the voltage. If the voltage at the junction is greater than the comparator threshold (usually one-half of the supply voltage), a 0 bit appears at the comparator output and is also stored in an output register. If the voltage at the junction is less than the threshold, a 1 bit appears at the comparator output and is stored in the output register.

If a 1 bit occurs, capacitor C remains connected to VREF throughout the remainder of the conversion. The process continues by connecting the C/2 capacitor from ground to VREF, and the comparison again takes place and another output bit is generated. This process continues until all capacitor voltages have been compared. During this process, the initial charges on the capacitors are redistributed according to the value of the input voltage.

The binary output appears in the successive-approximations register. The circuit is easily expanded with more capacitors to produce a greater number of output bits. Both positive and negative reference voltages can be used to accommodate a bipolar input signal. A switched-capacitor network makes the A/D converter very small. It can then be easily integrated into other circuits. A typical case is an A/D converter integrated into a microcontroller chip with memory.

**Flash Converters**

A flash converter takes an entirely different approach to the A/D conversion process. It uses a large resistive voltage divider and multiple analog comparators. The number of comparators required is equal to 2N – 1, where N is the number of desired output bits. A 3-bit A/D converter requires 23 – 1 = 8 – 1 = 7 comparators (see Fig. 7-22). The resistive voltage divider divides the dc reference voltage range into a number of equal increments. Each tap on the voltage divider is connected to a separate analog comparator. All the other comparator inputs are connected together and driven by the analog input voltage.

Some comparators will be on and others will be off, depending on the actual value of input voltage. The comparators operate in such a way that if the analog input is greater than the reference voltage at the divider tap, the comparator output will be binary 1. For example, if the analog input voltage in Fig. 7-22 is 4.5 V, the outputs of comparators 4, 5, 6, and 7 will be binary 1. The other comparator outputs will be binary 0. The encoder logic, which is a special combinational logic circuit, converts the 7-bit input from the comparators to a 3-bit binary output. Successive-approximations converters generate their output voltage after the circuits go through their decision-making process.

The flash converter, on the other hand, produces a binary output almost instantaneously. Counters do not have to be incremented, and a sequence of bits in a register does not have to be turned on and off. Instead, the flash converter produces an output as fast as the comparators can switch and the signals can be translated to binary levels by the logic circuits. Comparator switching and logic propagation delays are extremely short. Flash converters, therefore, are the fastest type of A/D converter. Conversion speeds of less than 100 ns are typical, and speeds of less than 0.5 ns are possible.

Flash speeds are given in MSPS or giga samples per second (GSPS) or 109 samples per second. Flash A/D converters are complicated and expensive because of the large number of analog comparators required for large binary numbers. The total number of comparators required is based upon the power of 2. An 8-bit flash converter has 2^8 – 1 = 255 comparator circuits. Obviously, ICs requiring this many components are large and difficult to make.

They also consume much more power than a digital circuit because the comparators are linear circuits. Yet for high-speed conversions, they are the best choice. With the high speed they can achieve, high-frequency signals such as video signals can be easily digitized. Flash converters are available with output word lengths of 6, 8, and 10.

b The voltage range of an A/D converter that uses 14-bit numbers is 26 to 16 V. Find (a) the number of discrete levels (binary codes) that are represented, (b) the number of voltage increments used to divide the total voltage range, and (c) the resolution of digitization expressed as the smallest voltage increment.

**Pipelined Converters**

A pipelined converter is one that uses two or more lower solution flash converters to achieve higher speed and higher resolution than successive approximations converters but less than a full fl ash converter. High-resolution flash converters with more than 8 bits are essentially impractical because the large number of comparators required makes the power consumption very high. However, it is possible to use several flash converters with a smaller bit count to achieve very high conversion speeds and higher resolution. An example is the two-stage 8-bit pipeline converter shown in Fig. 7-23.

The sampled analog input signal from a sample/hold (S/H) amplifier is applied to a 4-bit flash converter that generates the 4 most significant bits. These bits are applied to a 4-bit DAC and converted back to analog. The DAC output signal is then subtracted from the original analog input signal in a differential amplifier. The residual analog signal represents the least significant part of the signal. It is amplified and applied to a second 4-bit flash converter. Its output represents the 4 least significant bits of the output. With just two 4-bit flash converters, only 30 comparators are needed to achieve an 8-bit resolution. Otherwise, it would take 255 comparators, as indicated earlier. The tradeoff here is lower speed. A pipelined converter is obviously slower because it has to undergo a two-step conversion, one in each flash converter. However, the overall result is still very fast, much faster than that of any successive-approximations converter. This principle can be extended to three, four, or more pipeline stages to achieve resolutions of 12, 14, and 16-bits. Speeds as high as 10 GSPS are possible with this arrangement.

**ADC Specifications**

The key ADC specifications are speed, resolution, dynamic range, signal-to-noise ratio, effective number of bits, and spurious free dynamic range. Speed is the fastest sampling rate the ADC can achieve. Lower rates may be used. Modern ADCs can sample at rates to 20 GSPS.

Resolution is related to the number of bits. Resolution indicated the smallest input voltage that is recognized by the converter and is the reference voltage VREF divided by 2N, where N is the number of output bits. ADCs with resolutions of 8, 10, 12, 14, 16, 18, 20, 22, and 24 are used in a wide range of applications.

Dynamic range is a measure of the range of input voltages that can be converted. It is expressed as the ratio of the maximum input voltage to the minimum recognizable voltage and converted to decibels. In any ADC, the minimum input voltage is simply the value of the LSB voltage or 1. The maximum input is simply related to the maximum output code or 2^N – 1, where N is the number of bits. Therefore, you can express the dynamic range with the expression.

The greater the decibel value, the better. The signal-to-noise (S/N) ratio (SNR) plays a major part in the performance of an ADC. This is the ratio of the actual input signal voltage to the total noise in the system. The noise comes from a combination of clock-related noise, power supply ripple, external signal coupling, and quantizing noise. The clock noise can be minimized by locating clock wiring away from the ADC and minimizing jitter on the clock signal. Good bypassing on the power supply should take care of most ripple noise.

Then shielding the converter will reduce signals coupled in by inductive or capacitive coupling. Quantizing noise is another matter altogether. It is the result of the conversion process itself and cannot be reduced beyond a certain point. Quantizing noise is an actual voltage that manifests itself as noise added to the analog input signal as the result of the error produced in converting an analog signal to its closest digital value. You can see this error if you plot it over the input voltage range, as shown in Fig. 7-24. This figure is a plot showing the input voltage and the related output code in a simple 3-bit ADC. The 1-LSB resolution is VR/2N.

Below the plot is the noise or error voltage. When the ADC input voltage is exactly equal to the voltage represented by each output code, the error is zero. But as the voltage difference between the actual input voltage and the voltage represented by the code becomes greater, the error voltage increases. The result is a sawtooth like error voltage that in effect becomes noise added to the input signal. Luckily, the maximum noise peak is just 1 LSB, but that can reduce the conversion accuracy depending upon the input signal level. Quantization noise can be reduced by using a converter with a greater number of bits, as this reduces the maximum noise represented by the LSB value.

Another way to show quantizing noise is given in Fig. 7-25. If you could take the binary output of the ADC and convert it back to analog in a DAC and then show a frequency-domain plot of the result, this is what you would see. The noise, which is mostly quantizing noise, has multiple frequency components over a wide frequency range. The large vertical line represents the analog input signal voltage being converted. This plot also shows the signal-to-noise ratio in decibels. The rms value of the signal voltage and the average rms value of the noise are used in computing the decibel value of the SNR. A related specification is spurious free dynamic range (SFDR). See Fig. 7-26. It is the ratio of the rms signal voltage to the voltage value of the highest “spur” expressed in decibels.

A spur is any spurious or unwanted signal that may result from intermodulation distortion. This is the formation of signals that are the result of mixing or modulation action caused by any nonlinear characteristic of the converter circuitry, an amplifier, or related circuit or component. The spurs are sums or differences between the various signals present and their harmonics. As you might suspect, any noise, harmonics, or spurious signals all add together and basically reduce the resolution of an ADC. Often the combined noise level is greater than the LSB value, so only those more significant bits really define the signal amplitude. This effect is expressed by a measure known as the effective number of bits (ENOB). ENOB is computed with the expression.

SINAD is the ratio of the signal amplitude to all the noise plus harmonic distortion in the circuit. SINAD in a totally noise- and distortion-free ADC is 6.02N – 1.76, where N is the number of bits of resolution. This is the best SINAD figure possible, and it will be less in a practical converter.

**Example 7-4 1. **Calculate the SINAD for a 12-bit converter.

2. Calculate the ENOB for a converter with a SINAD of 78 dB.

**Solution **1. SINAD = 6.02(12) + 1.76 = 74 dB

2. ENOB = (78 – 1.76)/6.02 = 12.66 bits, or just 12 bits.

**Sigma-Delta Converter**

Another popular form of ADC is the sigma-delta (o¢) converter. Also known as a delta-sigma or charge balance converter, this circuit provides extreme precision, wide dynamic range, and low noise compared to other converters. It is available with output word lengths of 18, 20, 22, and 24 bits. These converters are widely used in digital audio applications, for example, CD, DVD, and MP3 players, as well as in industrial and geophysical applications where low-speed sensor data is to be captured and digitized.

They are not designed for high speed, nor are they adaptable to applications in which many separate channels must be multiplexed into one. The o¢ converter is what is known as an oversampling converter. It uses a clock or sampling frequency that is many times the minimum Nyquist rate required for other types of converters. Conversion rates are typically 64 to 128 times or more the highest frequency in the analog input signal.

For example, assume a music signal with harmonics up to 24 kHz. A successive-approximations converter would have to sample this at a rate of two or more times (more than 48 kHz) to avoid aliasing and loss of data. A o¢ converter would use a clock or sampling rate in the 1.5- to 3-MHz range. Sampling rates of several hundred times the highest input signal have been used. The reason for this is that the quantizing noise is reduced by a factor equal to the square root of the oversampling ratio.

The higher the sampling frequency, the lower the noise and as a result the wider the dynamic range. The oversampling techniques used in the sigma-delta converter essentially translate the noise to a higher frequency that can be easily filtered out by a low-pass filter. With a lower noise level, lower input levels can be converted, giving the converter extra dynamic range. Remember, the dynamic range is the difference between the lowest and the highest signal voltage levels that the converter can resolve, expressed in decibels. Of course, the other benefit of this technique is that aliasing is no longer a big problem. Often only a simple RC low-pass filter is needed to provide adequate protection from aliasing effects.

Fig. 7-27 shows the basic o¢ circuit. The input is applied to a differential amplifier that subtracts the output voltage of a 1-bit D/A converter from the input signal. This D/A converter is driven by the comparator output. If the output is a binary 1, the D/A converter outputs 11 V. If the comparator output is binary 0, the D/A converter outputs a 21 V. This sets the input voltage range to 11 V. The output of the differential amplifier is averaged in an integrator. The integrator output is compared to ground (0 V) in the comparator. The comparator is clocked by an external clock oscillator so that the comparator produces one output bit decision for each clock cycle.

The resulting bit stream of binary 0s and 1s represents the varying analog input signal. This serial bit stream is fed to a digital filter or decimator that produces the final binary output word. As the input signal is applied, the o¢ converter produces a serial bit stream output that represents the average value of the input. The closed-loop circuit causes the input signal to be compared to the D/A converter output every clock cycle, resulting in a comparator decision that may or may not change the bit value or the D/A converter output.

If the input signal is increasing, the D/A converter will continually output binary 1s so that the average in the integrator increases. If the input signal decreases, the comparator switches to binary 0, forcing the D/A converter output to -1 V. What happens is that the D/A converter output, averaged over many cycles, produces an output that equals the input voltage. The closed loop continually tries to force the differential amplifier output to zero.

To clarify, consider the D/A converter output that switches between +1 and -1 V. If the output is all binary 1s or +1-V pulses, the average value at the D/A converter output is just +1. If the D/A converter input is all binary 0s, then a series of -1-V pulses occur, making the output average -1 V over many cycles. Now assume that the D/A converter input is a series of alternating binary 0s and 1s. The D/A converter output is +1 V for one cycle and -1 V for the next cycle. The average over time is zero. Now you can see that with more binary 1s at the D/A converter input, the average output will rise above zero.

With a stream of more binary 0s, the average will become negative. The density of the 0s or 1s determines the average output value over time. The output of the comparator, then, is a bit stream that represents the average of the input value. It is a continuous non binary output. This serial bit stream is not very useful as is. Therefore, it is passed through a digital filter called a decimator. This filter uses digital signal processing (DSP) techniques that are beyond the scope of this book. But the overall effect of the filter is to digitally average the serial bit stream and to produce multibit sequential output words that are in effect a rolling average of the input. The filter or decimator produces binary outputs at some fraction of the clock rate. The overall result is as if the input signal were sampled at a much lower rate but with a very high-resolution converter. The true binary output words may be in serial or parallel form.

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Reference: Electronic communication by Louis Frenzel